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| T89C51RB2/RC2 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH 1. Description T89C51RB2/RC2 is a high performance FLASH version of the 80C51 8-bit microcontrollers. It contains a 16K or 32Kbytes Flash memory block for program and data. The 16 Kbytes or 32 Kbytes FLASH memory can be programmed either in parallel mode or in serial mode with the ISP capability or with software. The programming voltage is internally generated from the standard VCC pin. The T89C51RB2/RC2 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-source 4-level interrupt controller and three timer/counters. In addition, the T89C51RB2/RC2 has a Programmable Counter Array, an XRAM of 1024 byte, a Hardware Watchdog Timer, a Keyboard Interface, a SPI Interface, a more versatile serial channel that facilitates multiprocessor communication (EUART) and a speed improvement mechanism (X2 mode). Pinout is the standard 40/44 pins of the C52. The fully static design of the T89C51RB2/RC2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T89C51RB2/RC2 has 2 software-selectable modes of reduced activity and 8 bit clock prescaler for further reduction in power consumption. In the Idle mode the CPU is frozen while the peripherals and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. The added features of the T89C51RB2/RC2 make it more powerful for applications that need pulse width modulation, high speed I/O and counting capabilities such as alarms, motor control, corded phones, smart card readers. 2. Features * 80C52 Compatible * 8051 pin and instruction compatible * Four 8-bit I/O ports * Three 16-bit timer/counters * 256 bytes scratch pad RAM * 10 Interrupt sources with 4 priority levels * Dual Data Pointer * On-chip 1024 bytes expanded RAM (XRAM) * Software selectable size (0, 256, 512, 768, 1024 bytes) * 256 bytes selected at reset for TS87C51RB2/RC2 compatibility * Variable length MOVX for slow RAM/peripherals * ISP (In System Programming) using standard VCC power supply. * * * * Keyboard interrupt interface on port P1 SPI Interface (Master / Slave Mode) 8-bit clock prescaler Improved X2 mode with independant selection for CPU and each peripheral * * * * High Speed Output, Compare / Capture, Pulse Width Modulator, Watchdog Timer Capabilities * Boot ROM contains low level FLASH programming routines and a default serial loader * 40 MHz in standard mode * 20 MHz in X2 mode (6 clocks/machine cycle) * Programmable Counter Array 5 Channels with: * High-Speed Architecture * 16K/32K bytes on-chip FLASH program / data Memory * Byte and page (128 bytes) erase and write * 100k write cycles * * * * Asynchronous port reset Full duplex Enhanced UART Dedicated Baud Rate Generator for UART Low EMI (inhibit ALE) Rev. B - 30-Mar-01 1 Preliminary T89C51RB2/RC2 * Hardware Watchdog Timer (One-time enabled with Reset-Out) * Power control modes: * Idle Mode. * Power-down mode. - 50A at 3V - 100A Commercial at 5V - 150A Industrial at 5V * Power-Off Flag. * Power supply: 4.5 to 5.5V or 2.7 to 3.6V * Temperature ranges: Commercial (0 to +70C) and industrial (-40C to +85C). * Packages: PDIL40, PLCC44, VQFP44 Table 1. Memory Size Flash (bytes) T89C51RB2 T89C51RC2 16k 32k XRAM (bytes) 1024 1024 TOTAL RAM (bytes) 1280 1280 I/O 32 32 3. Block Diagram T2EX PCA RxD TxD VCC ECI Vss (2) (2) XTAL1 XTAL2 Boot ROM 2Kx8 (1) (1) (1) (1) EUART + BRG RAM 256x8 Flash 32Kx8 or 16Kx8 XRAM 1Kx8 PCA Timer2 ALE/ PROG PSEN CPU C51 CORE IB-bus EA RD WR (2) (2) Timer 0 Timer 1 INT Ctrl Parallel I/O Ports & Ext. Bus Port 0 Port 1 Port 2 Port 3 Port I2 Watch Key Dog Board SPI (2) (2) T0 T1 RESET (2) (2) INT0 INT1 PI2 P1 P2 P0 P3 MISO T2 (1) (1) (1) (1) MOSI SCK (1): Alternate function of Port 1 (2): Alternate function of Port 3 2 Rev. B - 30-Mar-01 Preliminary SS T89C51RB2/RC2 4. SFR Mapping The Special Function Registers (SFRs) of the T89C51RB2/RC2 fall into the following categories: * C51 core registers: ACC, B, DPH, DPL, PSW, SP * I/O port registers: P0, P1, P2, P3 * Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H * Serial I/O port registers: SADDR, SADEN, SBUF, SCON * PCA ( Programmable Counter Array ) registers : CCON , CCAPMx , CL , CH , CCAPxH , CCAPxL (x : 0 to 4) * Power and clock control registers: PCON * Hardware Watchdog Timer registers : WDTRST, WDTPRG * Interrupt system registers: IE0, IPL0, IPH0 , IE1 , IPL1 , IPH1 * Keyboard Interface registers : KBE , KBF , KBLS * SPI registers : SPCON , SPSTR , SPDAT * BRG ( Baud Rate Generator ) registers : BRL , BDRCON * Flash register : FCON * Clock Prescaler register : CKRL * Others: AUXR, AUXR1 , CKCON0 , CKCON1 Rev. B - 30-Mar-01 3 Preliminary T89C51RB2/RC2 Table 2. Sfr mapping Table below shows all SFRs with their address and their reset value. Bit Non Bit addressable addressable 0/8 F8h F0h E8h E0h D8h D0h C8h C0h B8h B0h A8h A0h 98h 90h 88h 80h IPL0 X000 000 P3 1111 1111 IE0 0000 0000 P2 1111 1111 SCON 0000 0000 P1 1111 1111 TCON 0000 0000 P0 1111 1111 0/8 TMOD 0000 0000 SP 0000 0111 1/9 TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B TH0 0000 0000 TH1 0000 0000 AUXR XX0X 0000 SADEN 0000 0000 IE1 XXXX X000 SADDR 0000 0000 IPL1 XXXX X000 IPH1 XXXX X111 ACC 0000 0000 CCON 00X0 0000 PSW 0000 0000 T2CON 0000 0000 CMOD 00XX X000 FCON (1) XXXX 0000 T2MOD XXXX XX00 CCAPM0 X000 0000 CCAPM1 X000 0000 CCAPM2 X000 0000 CCAPM3 X000 0000 CCAPM4 X000 0000 B 0000 0000 CL 0000 0000 CCAP0L CCAP1L CCAPL2L CCAPL3L CCAPL4L XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1/9 CH 0000 0000 2/A 3/B 4/C 5/D 6/E CCAP0H CCAP1H CCAPL2H CCAPL3H CCAPL4H XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 7/F FFh F7h EFh E7h DFh D7h RCAP2L 0000 0000 RCAP2H 0000 0000 SPCON 0001 0100 TL2 0000 0000 SPSTA 0000 0000 TH2 0000 0000 SPDAT XXXX XXXX CFh C7h BFh IPH0 B7h X000 0000 CKCON1 AFh XXXX XXX0 WDTRST WDTPRG A7h XXXX XXXX XXXX X000 KBLS 0000 0000 KBE 0000 0000 KBF 0000 0000 CKRL 1111 1111 CKCON0 0000 0000 PCON 00X1 0000 7/F 9Fh 97h 8Fh 87h AUXR1 XXXX X0X0 SBUF XXXX XXXX BRL 0000 0000 BDRCON XXX0 0000 4/C 5/D 6/E reserved (1) FCON access is reserved for the FLASH API and ISP software. 4 Rev. B - 30-Mar-01 Preliminary T89C51RB2/RC2 5. Pin Configurations P1.0/T2 P1.1/T2EX/SS P1.2/ECI P1.3CEX0 P1.4/CEX1 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7CEX4/MOSI RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 P1.1/T2EX/SS EA ALE/PROG P1.4/CEX1 PSEN P2.7/AD15 P2.6/AD14 P2.5/AD13 P2.4/AD12 P2.3/AD11 P2.2/AD10 P2.1/AD9 P2.0/AD8 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEx4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 P3.6/WR NIC* P2.0/A8 XTAL2 XTAL1 P2.2/A10 P0.0/AD0 P0.1/AD1 P0.2/AD2 P0.3/AD3 PDIL40 P1.3/CEX0 6 5 4 3 2 1 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 PLCC44 P1.1/T2EX/SS P1.4/CEX1 P1.3/CEX0 P1.2/ECI P1.0/T2 NIC* 44 43 42 41 40 39 38 37 36 35 34 P1.5/CEX2/MISO P1.6/CEX3/SCK P1.7/CEX4/MOSI RST P3.0/RxD NIC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 EA NIC* ALE/PROG PSEN P2.7/A15 P2.6/A14 P2.5/A13 VQFP44 1.4 12 13 14 15 16 17 18 19 20 21 22 XTAL2 XTAL1 NIC* P2.0/A8 P2.3/A11 P2.4/A12 P3.6/WR P3.7/RD P2.1/A9 VSS P2.2/A10 *NIC: No Internal Connection Rev. B - 30-Mar-01 VCC P2.3/A11 P2.4/A12 P3.7/RD P2.1/A9 VSS P0.2/AD2 P0.3/AD3 P0.0/AD0 P0.1/AD1 P1.2/ECI P1.0/T2 NIC* VCC 5 Preliminary T89C51RB2/RC2 Table 3. Pin Description for 40/44 pin packages Pin Number Mnemonic VSS VCC P0.0-P0.7 DIL 20 40 39-32 LCC 22 44 43-36 VQFP44 1.4 16 38 37-30 Type I I I/O Name and Function Ground: 0V reference Power Supply: This is the power supply voltage for normal, idle and power-down operation Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. Port 0 must be polarized to VCC or VSS in order to prevent any parasitic current consumption. Port 0 is also the multiplexed low-order address and data bus during access to external program and data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0 also inputs the code bytes during FLASH programming. External pull-ups are required during program verification during which P0 outputs the code bytes. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally pulled low will source current because of the internal pullups. Port 1 also receives the low-order address byte during memory programming and verification. Alternate functions for T89C51RB2/RC2 Port 1 include: P1.0 : Input / Output T2 (P1.0): Timer/Counter 2 external count input/Clockout P1.1 : Input / Output T2EX : Timer/Counter 2 Reload/Capture/Direction Control SS : SPI Slave Select P1.2 : Input / Output ECI : External Clock for the PCA P1.3: Input / Output CEX0 : Capture/Compare External I/O for PCA module 0 P1.4 : Input / Output CEX1 : Capture/Compare External I/O for PCA module 1 P1.5 : Input / Output CEX2 : Capture/Compare External I/O for PCA module 2 MISO : SPI Master Input Slave Output line When SPI is is in master mode , MISO receives data from the slave peripheral. When SPI is in slave mode , MISO outputs data to the master controller. P1.6 : Input / Output CEX3 : Capture/Compare External I/O for PCA module 3 SCK : SPI Serial Clock SCK outputs clock to the slave peripheral P1.7 : Input / Output: CEX4 : Capture/Compare External I/O for PCA module 4 MOSI : SPI Master Output Slave Input line When SPI is is in master mode , MOSI outputs data to the slave peripheral. When SPI is in slave mode , MOSI receives data from the master controller. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier P1.0-P1.7 1-8 2-9 40-44 1-3 I/O 1 2 2 3 40 41 3 4 5 6 4 5 6 7 42 43 44 1 I/O I/O I/O I I I/O I I/O I/O I/O I/O I/O I/O I/O 7 8 2 I/O I/O I/O I/O I/O I/O 8 9 3 XTAL1 XTAL2 19 18 21 20 15 14 I O 6 Rev. B - 30-Mar-01 Preliminary T89C51RB2/RC2 Pin Number Mnemonic P2.0-P2.7 DIL 21-28 LCC 24-31 VQFP44 1.4 18-25 Type I/O Name and Function Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally pulled low will source current because of the internal pullups. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order address bits during EPROM programming and verification: P2.0 to P2.5 for 16Kb devices P2.0 to P2.6 for 32Kb devices Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally pulled low will source current because of the internal pullups. Port 3 also serves the special features of the 80C51 family, as listed below. RXD (P3.0): Serial input port TXD (P3.1): Serial output port INT0 (P3.2): External interrupt 0 INT1 (P3.3): External interrupt 1 T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to V CC. This pin is an output when the hardware watchdog forces a system reset. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during Flash programming. ALE can be disabled by setting SFR's AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches. Program Strobe ENable: The read strobe to external program memory. When executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to FFFFH (RD). If security level 1 is programmed, EA will be internally latched on Reset. P3.0-P3.7 10-17 11, 13-19 5, 7-13 I/O 10 11 12 13 14 15 16 17 RST ALE/PROG 9 30 11 13 14 15 16 17 18 19 10 33 5 7 8 9 10 11 12 13 4 27 I O I I I I O O I/O O (I) PSEN 29 32 26 O EA 31 35 29 I Rev. B - 30-Mar-01 7 Preliminary T89C51RB2/RC2 6. Ordering Information T 89C51Rx2 -3C S C M Packages: 3C: PDIL40 SL: PLCC44 RL: VQFP44 (1.4mm) Temperature Range C:Commercial 0 to 70oC I:Industrial -40 to 85oC 89C51RC2 ( 32k Flash ) 89C51RB2 ( 16k Flash ) -M: VCC: 5V 40 MHz, X1 mode 20 MHz, X2 mode VCC: 3 V 40 MHz, X1 mode 20 MHz, X2 mode -L: Conditioning S: Stick T: Tray B: Blue Tape W: Wafer Rev. B - 30-Mar-01 8 Preliminary T89C51RB2/RC2 Table 4. Possible order entries Extension -3CSCM Stick, PDIL40, Com, 5V -3CSIM -SLSIM -SLSCL -SLSIL -RLTIM -RLTCL -SLSEM Stick, PDIL40, Ind, 5V Stick, PLCC44, Ind, 5V Stick, PLCC44, Com, 3V Stick, PLCC44, Ind, 3V Tray, VQFP44, Ind, 5V Tray, VQFP44, Com, 3V Stick, PLCC44, Sample, 5V -SLSCM Stick, PLCC44, Com, 5V Type T89C51RB2 T89C51RC2 X X X X X X X X X X X X X X X X X X 9 Rev. B - 30-Mar-01 Preliminary |
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